Field of Invention
The field of invention relates generally to computing system architecture, and, more specifically, to an asymmetric performance multicore architecture with same instruction set architecture (ISA).
Background
FIG. 1 shows a typical multi-core processor 100_1. As observed in FIG. 1, the multi-core processor 100_1 includes a plurality of processor cores 101_1 to 101_N on a same semiconductor die 100_1. Each of the processor cores typically contain at least one caching layer for caching data and/or instructions. A switch fabric 102 interconnects the processor cores 101_1 to 101_N to one another and to one or more additional caching layers 103_1 to 103_N. According to one approach, the processors 101_1 to 101_N and the one or more caching layers have internal coherency logic to, for example, prevent two different cores from concurrently modifying the same item of data.
A system memory interface (which may also include additional coherency logic) 104 is also included. Here, if a core requests a specific cache line having a needed instruction or item of data, and, the cache line is not found in any of the caching layers, the request is presented to the system memory interface 104. If the looked for cache line is not in the system memory 105_1 that is directly coupled to interface 104, the request is forwarded through system network interface 106 to another multi-core processor to fetch the desired data/instruction from its local system memory (e.g., system memory 105_X of multi-core processor 100_X). A packet switched network 107 exists between the multi-processor cores 100_1 to 100_X to support these kinds of system memory requests.
Interfaces to system I/O components 108_1 to 108_Y (e.g., deep non volatile storage such as a hard disk drive, printers, external network interfaces, etc.) are also included on the multi-processor core. These interfaces may take the form of high speed link interfaces such as high speed Ethernet interfaces and/or high speed PCIe interfaces.
Some multi core processors may also have a port 105 to the switch fabric 102 to scale upwards the number of processor cores associated with a same (also scaled upward) caching structure. For example, as observed FIG. 1, multi-processor cores 101_1 and 101_2 are coupled through the switch fabric port 105 to effectively form a platform of 2N cores that share a common caching structure (processor 100_2 is coupled to processor 100_1 through a similar port to its switch fabric).